? semiconductor components industries, llc, 2012 may, 2012 ? rev. 3 1 publication order number: NB3N511/d NB3N511 3.3v / 5.0v 14 mhz to 200 mhz pll clock multiplier description the NB3N511 is a clock multiplier that will generate one of nine selectable output multiples of an input frequency via two 3 ? level select inputs (s0, s1). it accepts a standard fundamental mode crystal or an external reference clock signal. phase ? locked ? loop (pll) design techniques are used to produce a low jitter, ttl level clock output up to 200 mhz with a 50% duty cycle. an output enable (oe) pin is provided, and when asserted low, the clock output goes into tri ? state (high impedance). the NB3N511 is commonly used in electronic systems as a cost efficient replacement for crystal oscillators features ? clock output frequencies up to 200 mhz ? nine selectable multipliers of the input frequency ? operating range: v dd = 3.3 v 10% or 5.0 v 5% ? low jitter output of 25 ps one sigma (rms) ? zero ppm clock multiplication error ? 45% ? 55% output duty cycle ? ttl/cmos output with 25 ma ttl level drive ? crystal reference input range of 5 ? 32 mhz ? input clock frequency range of 1 ? 50 mhz ? oe, output enable with tri ? state output ? 8 ? pin soic ? industrial t emperature range ? 40 c to +85 c ? these are pb ? free devices m feedback v dd multiplier select s1 phase detector charge pump crystal oscillator p clkout gnd s0 vco ttl/ cmos output figure 1. NB3N511 logic diagram oe x1/iclk x2 c lx2 c lx1 crystal or clock soic ? 8 d suffix case 751 marking diagram http://onsemi.com 3n511 = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package 3n511 alyw 1 8 1 8 see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information
NB3N511 http://onsemi.com 2 table 1. clock multiplier select table s1* s0* clkout multiplier l l 4x input l m 5.333x input l h 5x input m l 2.5x input m m 2x input m h 3.333x input h l 6x input h m 3x input h h 8x input *pins s1 and s0 default to m when open l = gnd h = vdd m = open (unconnected; will default to vdd/2) figure 2. NB3N511 package pinout, 8 ? pin (150 mil) soic (top view) clkout s0 oe x2 x1/iclk v dd gnd s1 1 2 3 45 6 7 8 table 2. pin description pin # name i/o description 1 x1/iclk crystal or lvcmos/lvttl input crystal or external reference clock input 2 vdd power supply positive supply voltage 3 gnd power supply 0 v. ground. 4 s1 three level input multiplier select pin ? connect to v dd , gnd or float 5 clkout lvcmos/lvttl output clock output 6 s0 three level input multiplier select pin ? connect to v dd , gnd or float 7 oe lvcmos/lvttl input output enable. clkout is high impedance when oe is low. internal pullup 8 x2 crystal crystal input ? leave open when providing an external clock reference table 3. common output frequency examples output frequency (mhz) input frequency (mhz) s1, s0 20 10 m, m 24 12 m, m 30 10 h, m 32 16 m, m 33.33 16.66 m, m 37.5 15 m, l 40 10 l, l 48 12 l, l 50 20 m, l 60 10 h, l 64 16 l, l table 4. common output frequency examples output frequency (mhz) input frequency (mhz) s1, s0 66.66 20 m, h 72 12 h, l 75 25 h, m 80 10 h, h 83.33 25 m, h 90 15 h, l 100 20 l, h 120 15 h, h 125 25 l, h 133.3 25 l, m 150 25 h, l
NB3N511 http://onsemi.com 3 table 4. attributes characteristics value esd protection human body model machine model charged device model > 1 kv > 150 v > 1 kv rpu ? oe input pull ? up resistor 270 k moisture sensitivity (note 1) soic ? 8 level 1 flammability rating oxygen index: 28 to 34 ul 94 v 0 @ 0.125 in transistor count 9555 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 5. maximum ratings symbol parameter condition 1 condition 2 rating unit v dd positive power supply gnd = 0 v 7 v v io input and output voltages ? 0.5 v v io v dd + 0.5 v t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm soic ? 8 soic ? 8 190 130 c/w jc thermal resistance (junction ? to ? case) (note 2) soic ? 8 41 to 44 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB3N511 http://onsemi.com 4 table 6. dc characteristics v dd = 3.3 v 10% or 5.0 v 5% unless otherwise noted, gnd = 0 v, t a = ? 40 c to +85 c symbol characteristic min typ max unit v dd operating voltage v dd = 5 v v dd = 3.3 v 4.75 3.0 5.25 3.6 v i dd power supply current ? inputs and outputs open, clkout operating at 100 mhz (with 20 mhz crystal) v dd = 5 v v dd = 3.3 v 9 8 ma v oh output high voltage i oh = ? 4 ma cmos high v dd ? 0.4 v v oh output high voltage i oh = ? 25 ma ttl high 2.4 v v ol output low voltage i ol = 25 ma 0.4 v v ih input high voltage, iclk only (pin 1) v dd = 5 v v dd = 3.3 v (v dd / 2) + 1 (v dd / 2) + 0.7 v v il input low voltage, iclk only (pin 1) v dd = 5 v v dd = 3.3 v (v dd / 2) ? 1 (v dd / 2) ? 0.7 v v ih input high voltage, s0, s1 v dd ? 0.5 v v il input low voltage, s0, s1 0.5 v v ih input high voltage, oe (pin 7) 2.0 v v il input low voltage, oe (pin 7) 0.8 v c in input capacitance, s0, s1 and oe 4 pf i sc output short circuit current, clkout 70 ma nominal output impedance 20 table 7. ac characteristics v dd = 3.3 v 10% or 5.0 v 5% unless otherwise noted, gnd = 0 v, t a = ? 40 c to +85 c symbol characteristic min typ max unit f xtal crystal input frequency (note 3) 5 32 mhz f clkin clock input frequency 1 50 mhz f out output frequency range f outmin f in x multiplier f outmax v dd = 4.25 to 5.25 v (5.0 v 5%) v dd = 3.0 to 3.6 v (3.3 v 10%) 14 14 200 200 mhz dc output clock duty cycle at 1.5 v 45 50 55 % oe h output enable time, oe high to output on 50 ns oe l output disable time, oe low to tri ? state 50 ns t jitter (rms) period jitter (rms, 1 ) 25 ps t jitter (pk ? to ? pk) total period jitter, (peak ? to ? peak) 70 ps t r /t f output rise/fall time (0.8 v to 2.0 v) (measured with 15 pf load) 1 1.5 ns 3. the crystal should be fundamental mode, parallel resonant. do not use third overtone. for exact tuning when using a crystal, capacitors should be connected from pins x1/clk to gnd and x2 to gnd. the value of these capacitors is given by the following equation, wh ere c l is the specified crystal load capacitance: crystal capacitance (pf) = (c l ? 5) x 2. so, for a crystal with 16 pf load capacitance, use two 22 pf capacitors.
NB3N511 http://onsemi.com 5 applications information high frequency cmos/ttl oscillators the NB3N511, along with a low frequency fundamental mode crystal, can build a high frequency ttl output oscillator. for example, a 20 mhz crystal connected to the NB3N511 with the 5x output selected (s1 = l, s0 = h) produces an 100 mhz cmos/ttl output clock. decoupling and external components the NB3N511 requires a 0.01 f decoupling capacitor to be connected between v dd and gnd on pins 2 and 3. it must be connected close to the NB3N511 to minimize lead inductance. control input pins can be connected to device pins v dd or gnd, or to the v dd and gnd planes on the board. series termination resistor a 33 terminating resistor can be used next to the clk pin for trace lengths over one inch. crystal information the crystal used should be a fundamental mode (do not use third overtone), parallel resonant. crystal load capacitors should be connected from pins x1 to ground and x2 to ground to optimize the frequency accuracy, see figure 1. the total on chip capacitance is approximately 12 pf. a parallel resonant, fundamental mode cry stal should be used. the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short pcb traces (and no vias) between the crystal and device. crystal capacitors, if needed, must be connected from each of the pins x1 and x2 to ground. the value (in pf) of these crystal caps should equal (c l ? 12 pf) * 2. in this equation, c l = crystal load capacitance in pf. example: for a crystal with a 16 pf load capacitance, each crystal capacitor would be 8 pf [(16 ? 12) x 2 = 8]. table 8. recommended crystal parameters parameter value crystal cut fundamental at cut resonance parallel resonance load capacitance 18 pf operating range ? 40 to +85 c shunt capacitance 5 pf max equivalent series resistance (esr) 50 max correlation drive level 1.0 mw max ordering information device package shipping ? NB3N511dg soic ? 8 (pb ? free) 98 units / rail NB3N511dr2g soic ? 8 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB3N511 http://onsemi.com 6 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NB3N511/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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